(1) Field of the Invention
This invention relates generally to electronic interfaces and relates more specifically to two wire interfaces.
(2) Description of the Prior Art
The Inter-Integrated Circuit (I2C), also called two-wire interface (TWI) interface is a 2-wire interface for low speed communication between electrical components. The communication is always initiated from the master component. The destination of this communication or slave is selected by a unique device address or device ID transmitted at the beginning of the communication. Only the selected slave is allowed to answer the request of the master.
In complex systems it often happens that 2 devices have the same device address or are even equal components with the same device address. In this case a master's request has always more than one slave, which is reacting. This causes violations on the bus and makes a communication impossible.
Possible solutions to solve these violations are:    1. Device dependent, hard coded slave address selection:            The usage of an extra input or inputs to a device allows selecting between different slave addresses the device is reacting on. Using equal devices on the same bus are then distinguishable if the slave address selection input is set different.        Disadvantage:        a. There need to be an extra pin on the component in case the slave address selection is controlled from the system. As these devices are getting smaller and smaller additional pins/pads are not desirable.        b. There is no extra input pin to the device in case the slave address selection input is hard wired in the device (e.g. chip bonding option). Having this scenario, identical devices cannot be exchanged; e.g. having a stereo camera system with 2 identical cameras there is a need to separate the cameras during manufacturing. The cameras need to be held separately and cannot be exchanged. This increase the logistic overhead for the system builds.        2. Programmable device address during startup:                    This mechanism allows programming the device address of a slave via software. Possible implementations are:                        a. Non-volatile memory in the device or component that contain the slave address selection. The slave address selection is read out by the device/component by its own at start up.                    Disadvantage: Need for none-volatile memory component in the device. In addition same disadvantage as under 1.b)                        b. Special startup strategy.                    To avoid that 2 slaves react on a given device ID the system could power up one device first and reprogram the device address (needs to be foreseen to allow reprogramming of slave address with the given control bus). The second device with the same slave address is not able to react on this request because it is not yet powered on. Thus no violation on the control bus can happen. After reprogramming the slave address of the first device the second one can be powered up. After this special startup the 2 devices can be differentiated.                        
Two Wire Interface—Overview
The TWI or I2C control bus uses 2 lanes, a serial data lane (SDA) and a serial clock lane (SCL). The data lane is used to transfer the information whereas the clock lane controls or validates the data information flow. It is realized as shown in FIG. 1 prior art.
Master and slave are connected to the Serial Data Line (SDA) and Serial Clock line (SCL) via an Open-Drain or Open-Collector circuit. This allows that several devices can access the bus in parallel. An Open-Drain/Open-Collector circuit is shown in FIG. 2 prior art.
An Open-Drain/Open-Collector circuit is shown in FIG. 2 prior art. For the Open-Drain or Open-Collector circuit the according bus line is pulled up to VDD via a pull-up resistor, while the device does only drive ‘0’ on the bus. The resulting signal level on the bus is an AND combination of the outputs of all devices connected to the line.
FIG. 3 prior art shows different states of the SDA and SCL lines i.e. when data line is stable and valid and when change of data is allowed. The data on the two serial lines of the I2C bus are transferred bit by bit. The data bit on the SDA line is valid during the SCL line is high. During this high period of the SCL line the SDA data line must be stable. If the SCL line is low state a change of the SDA data line is allowed and the SDA value is not valid.
As illustrated in FIG. 4 prior art the I2C bus defines special conditions called Start (S) and Stop (P) additionally to the bit transfer. The Start condition signals a start of data transfer whereas the stop condition terminates the bus transfer. A start condition occurs when there is a transition of the SDA line from high to low while the SCL line is high. A stop condition occurs if the SDA line goes from low to high while the SCL line is asserted.
The master device generates the Start and Stop conditions, whereas data transfer can happen in both directions (read/write). Instead of termination a bus transfer with the stop command an immediate new transfer can be started by the master with a repeated Start (SR) command as shown in FIG. 4 prior art. The repeated start command has the same characteristics as the normal Start condition.
The data transfer on the I2C bus, shown in FIG. 5 prior art, is done in byte packets (8 bit). The number of bytes that can be transmitted in a transfer cycle is not restricted. Each byte is transmitted with the most significant bit (MSB) first and each byte is followed by an acknowledge toggle bit (ACK). The device receiving the data bits sets the acknowledge bit (master sends data and the slave acknowledges or slave sends data and master acknowledges).
For the acknowledge clock cycle the receiver of the data byte must pull down the SDA line so that it is stable low during the high period of SCL. The acknowledge cycle occurs after each transmitted byte.
If a slave is not able to process a transfer or additional bytes it leaves the SDA line in high state (not acknowledge). In case of a write access the master has to start a new transfer to write the data byte that was not acknowledged. If the slave transmits data to the master (read access) the master has to not acknowledge the last byte of the transfer to signal the slave to release the data line. This allows the master to set a Stop or Restart condition. Anyway a not acknowledged byte is followed by a stop or restart condition of the master device in any case.
FIG. 6 prior art illustrates a possible data transfer terminology is mentioned as 7-bit addressing in the specification. This invention can also be expanded to other addressing modes like the ones also mentioned in [1] and [2]. In this mode a 7-bit address is sent by the master after the start/restart condition. This 7-bit address selects the slave to be accessed. The eighth bit of the first byte specifies the data transfer direction. A ‘0’ represent a write access whereas a ‘1’ indicates a read. Only the addressed slave, i.e. the slave with a transmitted and unique slave address is assigned to and is allowed to react or answer the access.
It is a challenge for engineers to differentiate identical devices on a two-wire interface.
There are known patents or patent publications dealing with master/slave communication of two wire interfaces:
U.S. Patent Publication (US 2009/0234999 to Huang et al.) teaches an apparatus for resolving conflicts happening between two I2C slave devices with the same addressed address. The apparatus is composed by all cheap electronic devices, so as to achieve a purpose of lowering a cost for design. In addition, in the apparatus for resolving conflicts happened between two I2C slave devices with the same addressed address of the invention, all the I2C slave devices are addressed by an I2C master device to perform the data transmission subsequently before a basic input/output system (BIOS) completes a power-on self-test (POST), but all the I2C slave devices are addressed by a system chip (for example, a baseboard management controller (BMC)) to perform the data transmission subsequently after the BIOS completes the POST. Therefore, the purpose of performing the data transmission for all the I2C slave devices on real time is achieved.
U.S. Patent Publication (US 2008/0288684 to Ellison) discloses a design structure to facilitate I2C communication between a host device and a slave device where the slave device shares a common physical address with another slave device on the I2C bus. The design structure includes an apparatus, which includes a detection module to detect an incoming address on the I2C bus, a translation module to translate the incoming address to an outgoing address, and a communication module to communicate data between the host device and the slave device where the outgoing address matches the physical address of the slave device. In this manner, address conflicts between commonly addressed slave devices can be avoided while reducing costs, components, and complexities traditionally associated with dynamic addressing techniques and other prior art solutions to address conflicts.
U.S. Patent (U.S. Pat. No. 7,444,453 to Ellison) discloses a method to facilitate I2C communication between a host device and a slave device where the slave device shares a common physical address with another slave device on the I2C bus. The method includes detecting an incoming address on the I2C bus, translating the incoming address to an outgoing address, and communicating data between the host device and the slave device where the outgoing address matches the physical address of the slave device. In this manner, the present invention avoids address conflicts between commonly addressed slave devices while reducing costs, components, and complexities traditionally associated with dynamic addressing techniques and other prior art solutions to address conflicts.
Furthermore two publications describe addressing schemes of two wire interfaces:                [1] UM10204, I2C-bus specification and user manual, Rev. 03-19 June 2007, NXP B.V,        [2] The I2C-bus specification; version 2.1, January 2000, Philips Semiconductors.        